Toshiba TLCS-900/H1 Series Manual page 450
Original cmos 32-bit microcontroller
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For reference, details of calculation flow are given below.
1)
Make XOR data by calculating exclusive OR after both ECC code from NDFC and
NAND flash are placed to 4-byte data as below.
Lower 2 bytes:
Upper 2 bytes:
2)
If XOR data equals "0", it will terminate normally because the ECC code is the
same, but if not, they are checked as to whether they are correctable or not.
3)
If XOR data does not have 2-bit or more "1" data, it will terminate normally
because of the ECC code 1-bit error.
4)
If the effective data (2-bit width from bit0 to bit21 in XOR data) equals either 01B
or 10B, it corrects data because they are correctable.
If the effective data has either 00B or 11B, it terminates abnormally because they
are not correctable.
Example 1: If the XOR data equals 0026A65AH, shown below in binary,
0000000000 10 01 10 10 10 01 10 01 01 10 10B
all effective data (2-bit width from bit0 to bit21) equals either 01B or 10B. So,
this is evaluated as being correctable.
Example 2: If the XOR data equals 002EA65AH, shown below in binary,
0000000000 10 11 10 10 10 01 10 01 01 10 10B
bit18 and bit19 are 11B, so this is evaluated as being uncorrectable.
5)
Data correcting takes error line information from line parity in XOR data and
error bit information from column parity and inverts the bit.
Example:
If the XOR data equals 0026A65AH, line parity is shown below in binary.
10 10 01 10 01 01 10 10B
If 10B is converted to 1B and 01B is converted to 0B,
they become 1 1 0 1 0 0 1 1B and meaning the 212th byte.
In the same manner, error bit information becomes bit5.
As a result, it inverts bit5 of 212th byte.
Line parity
Column parity
(Valid data of column parity is lower 6-bit in upper 2 bytes)
92CH21-448
TMP92CH21
2009-06-19
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