Toshiba TLCS-900/H1 Series Manual page 480
Original cmos 32-bit microcontroller
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(4) SDRAM burst read timing (End of burst cycle)
SDCLK
t
CMH
SDxxDQM
SDCS
SDRAS
SDCAS
SDWE
A1 to A11 or
Column
A1 to A10
A12 or A11
Column
A13 to A15 or
Row
A12 to A15
D0 to D31
t
CMS
t
CMS
t
CMS
t
CMH
t
AS
220
0
t
t
AC
AC
Data input
Data input
t
t
OH
OH
92CH21-478
t
CK
t
RSC
t
CMH
Data input
t
OH
TMP92CH21
t
RC
Column
Column
Column
2009-06-19
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