Toshiba TLCS-900/H1 Series Manual page 37

The operation of each of the different HALT modes is described in Table 3.3.4.
HALT Mode
SYSCR2<HALTM1:0>
CPU
I/O ports
TMRA, TMRB
SIO
AD converter
Block
WDT
I2S, LCDC, SDRAMC,
Interrupt controller,
USBC,
RTC, MLD
(2) How to release the HALT mode
These halt states can be released by resetting or requesting an interrupt. The halt
release sources are determined by the combination of the states of the interrupt mask
register <IFF2:0> and the HALT modes. The details for releasing the halt status are
shown in Table 3.3.5.
Release by interrupt requesting
The HALT mode release method depends on the status of the enabled
interrupt .When the interrupt request level set before executing the HALT
instruction exceeds the value of the interrupt mask register, the interrupt is
processed depending on its status after the HALT mode is released, and the CPU
status executing the instruction that follows the HALT instruction. When the
interrupt request level set before executing the HALT instruction is less than the
value of the interrupt mask register, HALT mode release is not executed. (in
non-maskable interrupts, interrupt processing is processed after releasing the
HALT mode regardless of the value of the mask register.) However only for INT0 to
INT4, INTKEY, INTRTC, INTALM and INTUSB interrupts, even if the interrupt
request level set before executing the halt instruction is less than the value of the
interrupt mask register, HALT mode release is executed. In this case, the interrupt
is processed, and the CPU starts executing the instruction following the HALT
instruction, but the interrupt request flag is held at "1".
Release by resetting
Release of all halt statuses is executed by resetting.
When the STOP mode is released by RESET, it is necessary to allow enough
resetting time (see Table 3.3.6) for operation of the oscillator to stabilize.
When releasing the HALT mode by resetting, the internal RAM data keeps the
state before the HALT instruction is executed. However the other settings contents
are initialized. (Releasing due to interrupts keeps the state before the HALT
instruction is executed.)
Table 3.3.4 I/O Operation during HALT Modes
IDLE2
11
Available to select
operation block
Operate
92CH21-35
IDLE1
10
Stop
Depend on PxDR register setting
Operate
TMP92CH21
STOP
01
Stop
2009-06-19