Toshiba TLCS-900/H1 Series Manual page 230

3.10.3.24 EPx_MODE Register (x: 1 to 3)
bit Symbol
EP1_MODE
(0789H)
Read/Write
Reset State
EP2_MODE bit Symbol
(078AH)
Read/Write
Reset State
EP3_MODE
bit Symbol
(078BH)
Read/Write
Reset State
Note1: When writing to this register, a recovery time of 5clocks at 12MHz is needed. After writing this register, insert
dummy instruction of 420 ns or longer.
Note2: When writing to this register, endpoint is initialized same as RESET of COMMAND register.
Note3: Max packet size of Isochronous transfer type is 1023 bytes.
Note4: IfwMaxPacketSize of descriptor was set to other than 8, 16, ..., 1023, Payload more than descriptor value is
set by auto-answer of Set_Configration and Set_Interface.
This register sets transfer mode of endpoint (EP1 to EP3).
If SET_CONFIG and SET_INTERFACE processing is set to software control, this
control must use appointed config or interface. Access this register to set mode.
7 6
7 6
7 6
There is a limitation to the timing that can be written.
If SET_CONFIG and SET_INTERFACE processing is set to software control, after
INT_SETUP interrupt is received, finish writing before accessing EOP register. This
register prohibits writing when it is timing, and it is ignored.
DIRECTION (Bit0)
0: OUT Direction from host to device
1: IN Direction from device to host
MODE [1:0] (Bit1 and bit2)
00: Control transfer type
01: Isochronous transfer type
10: Bulk transfer type or interrupt transfer type
11: Interrupt (No toggle)
Note: If setting endpoint that is set to Isochronous transfer mode to "no use", after changing to
Isochronous mode, set to "no use" by COMMAND register.
PAYLOAD [2:0] (Bit3, bit4 and bit5)
000: 8 bytes
001: 16 bytes
010: 32 bytes
011: 64 bytes
0100:128 bytes
0101:256 bytes
0110:512 bytes
0111:1023 bytes (Note1, 2)
Others (Bit6 and bit7) Reserved
5 4
Payload[2] Payload[1] Payload[0]
R/W R/W
0 0
5 4
Payload[2] Payload[1] Payload[0]
R/W R/W
0 0
5 4
Payload[2] Payload[1] Payload[0]
R/W R/W
0 0
92CH21-228
3 2 1
Mode[1] Mode[0]
R/W R/W R/W
0 0 0
3 2 1
Mode[1] Mode[0]
R/W R/W R/W
0 0 0
3 2 1
Mode[1] Mode[0]
R/W R/W R/W
0 0 0
TMP92CH21
0
Direction
R/W
0
0
Direction
R/W
0
0
Direction
R/W
0
2009-06-19