Toshiba TLCS-900/H1 Series Manual page 356

f
SYS
A23 to A0
RD
D31 to D0 or D16 to D0
8-bit bus
LCP0 (2CP)
LD7 to LD0
LCP0 (4CP)
LD7 to LD0
4-bit bus
LCP0 (2CP)
LD3 to LD0
227 Row
IN IN + 1 IN + 2
OUT + 1 OUT + 2 OUT + 3 OUT + 4
OUT
OUT + 1 OUT + 2 OUT + 3 OUT + 4 OUT + 5 OUT + 6
OUT
Figure 3.14.12 Timing Diagram of SDRAM Burst Run
92CH21-354
Column
IN + 3 IN + 4 IN + 5 IN + 6 IN +7
OUT + 5 OUT + 6
OUT + 1 OUT + 2
OUT
TMP92CH21
16-bit bus, monochrome
/4 grayscales/256 colors
32-bit bus, monochrome
/4 grayscales/256 colors
16-bit bus, 16 grayscales
16-bit bus, monochrome
/4/16 grayscales/256 colors
32-bit bus, monochrome
/4/16 grayscales/256 colors
2009-06-19