Toshiba TLCS-900/H1 Series Manual page 24

Original cmos 32-bit microcontroller

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Note: Ensure that the logic of PLLCR0<LUPFG> is different from 900/L1's DFM.

(Purpose and use)

This register is used to set each pin status at stand-by mode.

All ports have registers of the format shown above. ("x" indicates the port name.)

For each register, refer to "3.5 Function of ports".

Before "Halt" instruction is executed, set each register according to the expected pin-status. They will be effective

after the CPU has executed the "Halt" instruction.

This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP).

The output/input buffer control table is shown below.

Figure 3.3.5 SFR for PLL

Output/input buffer drive-register for stand-by mode

Output Buffer

Note 1: OE denotes an output enable signal before stand-by mode.

Basically, PxCR is used as OE.

Note 2: "n" in PxnD denotes the bit number of PORTx.

Figure 3.3.6 SFR for Drive Register

Input Buffer

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