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Toshiba TLCS-900/H1 Series Manual page 523

Original cmos 32-bit microcontroller
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(9) 8-bit timer
Symbol
Name
Address
TMRA01
TA01RUN
RUN
1100H
register
1102H
8-bit timer
TA0REG
(Prohibit
register 0
RMW)
1103H
8-bit timer
TA1REG
(Prohibit
register 1
RMW)
TMRA01
TA01MOD
mode
1104H
register
TMRA1
1105H
flip-flop
TA1FFCR
(Prohibit
control
RMW)
register
TMRA23
TA23RUN
RUN
1108H
register
110AH
8-bit timer
TA2REG
(Prohibit
register 2
RMW)
110BH
8-bit timer
TA3REG
(Prohibit
register 3
RMW)
TMRA23
TA23MOD
mode
110CH
register
TMRA3
110DH
flip-flop
TA3FFCR
(Prohibit
control
RMW)
register
7
6
5
TA0RDE
R/W
0
Double
buffer
0: Disable
1: Enable
TA01M1
TA01M0
PWM01
0
0
0
Operation mode
PWM cycle
00: 8-bit timer mode
00: Reserved
6
01: 16-bit timer mode
01: 2
7
10: 8-bit PPG mode
10: 2
8
11: 8-bit PWM mode
11: 2
TA1RDE
R/W
0
Double
buffer
0: Disable
1: Enable
TA23M1
TA23M0
PWM21
0
0
0
Operation mode
PWM cycle
00: 8-bit timer mode
00: Reserved
6
01: 16-bit timer mode
01: 2
7
10: 8-bit PPG mode
10: 2
8
11: 8-bit PWM mode
11: 2
92CH21-521
4
3
2
I2TA01
TA01PRUN TA1RUN
0
0
IDLE2
TMRA01
0: Stop
prescaler
1: Operate
0: Stop and clear
1: Run (Count up)
W
Undefined
W
Undefined
PWM00
TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0
R/W
0
0
0
Source clock for TMRA1
00: TA0TRG
01: φT1
10: φT16
11: φT256
TA1FFC1 TA1FFC0
W
1
1
00: Invert TA1FF
01: Set TA1FF
10: Clear TA1FF
11: Don't care
I2TA23
TA23PRUN
0
0
IDLE2
TMRA23
0: Stop
prescaler
1: Operate
0: Stop and clear
1: Run (Count up)
W
Undefined
W
Undefined
PWM20
TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0
R/W
0
0
0
Source clock for TMRA3
00: TA2TRG
01: φT1
10: φT16
11: φT256
TA3FFC1 TA3FFC0
W
1
1
00: Invert TA3FF
01: Set TA3FF
10: Clear TA3FF
11: Don't care
TMP92CH21
1
0
TA0RUN
R/W
0
0
UP counter
UP counter
(UC0)
(UC1)
0
0
Source clock for TMRA0
00: Reserved
01: φT1
10: φT4
11: φT16
TA1FFIE
TA1FFIS
R/W
0
0
TA1FF
TA1FF
control for
Inversion
inversion
select
0: Disable
0: TMRA0
1: Enable
1: TMRA1
TA3RUN
TA2RUN
R/W
0
0
UP counter
UP counter
(UC4)
(UC3)
0
0
Source clock for TMRA2
00: Reserved
01: φT1
10: φT4
11: φT16
TA3FFIE
TA3FFIS
R/W
0
0
TA3FF
TA1FF
control for
inversion
inversion
select
0: Disable
0: TMRA2
1: Enable
1: TMRA3
2009-06-19

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