Hitachi SH7750 Hardware Manual page 74

Table 1.3 Pin Functions (cont)
Pin
No. Pin Name I/O
31 VDDQ Power
32 VSSQ Power
33 D15 I/O
34 D0 I/O
35 D14 I/O
36 D1 I/O
37 D13 I/O
38 D2 I/O
39 VDD Power
40 VSS Power
41 D12 I/O
42 D3 I/O
43 VDDQ Power
44 VSSQ Power
45 D11 I/O
46 D4 I/O
47 D10 I/O
48 D5 I/O
49 D9 I/O
50 D6 I/O
BACK/
51 O
BSREQ
BREQ/
52 I
BSACK
53 D8 I/O
54 D7 I/O
55 CKE O
56 VDDQ Power
57 VSSQ Power
WE5/CAS5/
58 O
DQM5
Rev. 6.0, 07/02, page 24 of 986
Function Reset
IO VDD (3.3 V)
IO GND (0 V)
Data
Data
Data
Data
Data
Data
Internal VDD
(1.8 V)
Internal GND
(0 V)
Data
Data
IO VDD (3.3 V)
IO GND (0 V)
Data
Data
Data
Data
Data
Data
Bus
acknowledge/
bus request
Bus request/bus
acknowledge
Data
Data
Clock output
enable
IO VDD (3.3 V)
IO GND (0 V)
D47–D40 select
signal
Memory Interface
SRAM DRAM SDRAM PCMCIA MPX
CKE
WE5 CAS5
DQM5
A15
A0
A14
A1
A13
A2
A12
A3
A11
A4
A10
A5
A9
A6
A8
A7