Hitachi SH7750 Hardware Manual page 19

Section
22.3.4 Peripheral Module
Signal Timing
Appendix A Address List
Appendix B Package
Dimensions
Appendix C Mode Pin
Settings
Appendix D CKIO2ENB Pin
Configuration
Appendix E Pin Functions
Appendix F Synchronous
DRAM Address
Multiplexing Tables
Page Item
924, 925 Table 22.36 Peripheral
Module Signal Timing (1)
900 to Figures 22.37 to 22.58,
921, 923 Figure 22.60
930 Figure 22.62 RTC Oscillation
Settling Time at Power-On
Figure 22.66(b) DBREQ/TR
932
Input Timing and BAVL
Output Timing
937 to Table A.1 Address List
942
943, 944 Figure B.1 Package
Dimensions (256-Pin BGA)
Figure B.2 Package
Dimensions (208-Pin QFP)
946 Clock Modes
947 Area 0 Bus Width
Figure D.1 CKIO2ENB Pin
948
Configuration
950 to Table E.1 Pin States in
952 Reset, Power-Down State,
and Bus-Released State
970, 971 (17) BUS 64
(128M: 4M × 8b × 4) × 8
(SH7750R only)
(18) BUS 64
(256M: 4M × 16b × 4) × 4
(SH7750R only)
Description
Table newly added
Titles amended
Amended
Newly added
BCR4, RCR3, RYRAR,
SDINT and Notes
added
BCR3 area 7 address
amended
DMAC, INTC, CPG,
TMU table added
Amended
Table 10.3 (1), (2)
inserted
Area 0 memory type
deleted and data
integrated into area 0
bus width table
Amended
Sleep row deleted
D40–D51 deleted
Notes added
Newly added
Rev. 6.0, 07/02, page xix of I