Hitachi SH7750 Hardware Manual page 18

Section
22.3.1 Clock and Control
Signal Timing
22.3.2 Control Signal Timing 868
22.3.3 Bus Timing
Rev. 6.0, 07/02, page xviii of I
Page Item
850, 851 Table 22.28 Clock and
Control Signal Timing
(HD6417750RF200)
852, 853 Table 22.29 Clock and
Control Signal Timing
(HD6417750BP200M,
HD6417750SBP200)
854, 855 Table 22.30 Clock and
Control Signal Timing
(HD6417750SF200)
856, 857 Table 22.31 Clock and
Control Signal Timing
(HD6417750F167,
HD6417750F167I,
HD6417750SF167,
HD6417750SF167I)
858, 859 Table 22.32 Clock and
Control Signal Timing
(HD6417750SVF133,
HD6417750SVBT133)
860, 861 Table 22.33 Clock and
Control Signal Timing
(HD6417750VF128)
864 Figure 22.6 Standby Return
Oscillation Settling Time
(Return by RESET)
865 Figure 22.8 Standby Return
Oscillation Settling Time
(Return by IRL3–IRL0)
866 Figure 22.10 PLL
Synchronization Settling Time
in Case of IRL Interrupt
Table 22.34 Control Signal
Timing (1)
880 Figure 22.18 SRAM Bus
Cycle: Basic Bus Cycle (No
Wait, Address Setup/Hold
Time Insertion, AnS = 1,
AnH = 1)
881 Figure 22.19 Burst ROM
Bus Cycle (No Wait)
871, 872 Table 22.35 Bus Timing (1)
Description
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Newly added
Amended
Amended
Amended
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Amended
Table newly added
Figure changed and
Note added
Amended
Table newly added