Figure 13.22 (3) Dram Burst Bus Cycle, Ras Down Mode Start (Edo Mode, Rcd = 0, Anw = 0) - Hitachi SH7750 Hardware Manual

Tpc Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce
CKIO
r c1 c2 c3 c4
A25–A0
RD/
D63–D0
d1 d2 d3 d4
(read)
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start
(EDO Mode, RCD = 0, AnW = 0)
Rev. 6.0, 07/02, page 407 of 986