Hitachi SH7750 Hardware Manual page 41

Figure 14.54 DTR Format (Transfer Request Format) (SH7750R) ...................................... 584
Single Address Mode/Burst Mode/External Bus → External Device
Figure 14.55
32-Byte Block Transfer/Channel 0 On-Demand Data Transfer....................... 589
Single Address Mode/Burst Mode/External Bus → External Device/
Figure 14.56
32-Byte Block Transfer/On-Demand Data Transfer on Channel 4.................. 590
Figure 15.1 Block Diagram of SCI ..................................................................................... 595
Figure 15.2 MD0/SCK Pin.................................................................................................. 611
Figure 15.3 MD7/TxD Pin .................................................................................................. 612
Figure 15.4 RxD Pin............................................................................................................ 612
Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits)...................................................................................... 623
Figure 15.6 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode) ..................................................................................... 625
Figure 15.7 Sample SCI Initialization Flowchart................................................................ 626
Figure 15.8 Sample Serial Transmission Flowchart............................................................ 627
Figure 15.9 Example of Transmit Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)............................................. 629
Figure 15.10 Sample Serial Reception Flowchart (1) ........................................................... 630
Figure 15.10 Sample Serial Reception Flowchart (2) ........................................................... 631
Figure 15.11 Example of SCI Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)............................................. 633
Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)..................................... 635
Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart................................... 636
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit) ................................................................... 638
Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1) .................................. 639
Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2) .................................. 640
Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit) ................................................................... 641
Figure 15.17 Data Format in Synchronous Communication ................................................. 642
Figure 15.18 Sample SCI Initialization Flowchart................................................................ 644
Figure 15.19 Sample Serial Transmission Flowchart............................................................ 645
Figure 15.20 Example of SCI Transmit Operation ............................................................... 646
Figure 15.21 Sample Serial Reception Flowchart (1) ........................................................... 647
Figure 15.21 Sample Serial Reception Flowchart (2) ........................................................... 648
Figure 15.22 Example of SCI Receive Operation ................................................................. 649
Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception...................... 650
Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode................................. 654
Figure 15.25 Example of Synchronous Transmission by DMAC......................................... 655
Figure 16.1 Block Diagram of SCIF ................................................................................... 659
Figure 16.2 MD8/RTS2 Pin ................................................................................................ 681
CTS2 Pin.......................................................................................................... 682
Figure 16.3
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