Interrupt Source Register (Sdint) (Sh7750R Only); Boundary Scan Register (Sdbsr) (Sh7750R Only) - Hitachi SH7750 Hardware Manual

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Interrupt Source Register (SDINT) (SH7750R Only)

The interrupt source register (SDINT) is a 16-bit register that can be read from and written to by

From the H-UDI pins, the INTREQ bit is set to 1 when a H-UDI interrupt command is set in the

SDIR register (Update-IR). While SDIR is holding a H-UDI interrupt command, the SDINT

bit register. In this case, the upper 16 bits will all be 0, and the lower 16 bits will represent SDINT.

From the CPU, only writing a 0 to the INTREQ bit is possible. While this bit holds a 1, the

interrupt requests continue to be issued, so this bit should always be cleared in the interrupt

This register is initialized in the Test-Logic-Reset state of TRST or TAP.

Initial value:

Initial value:

Bits 15 to 1—Reserved: These bits are always read as 0. When writing, only 0s should be written

Bit 0    Interrupt Request (INTREQ): Indicates whether or not an interrupt request has been

issued by an H-UDI interrupt command. From the CPU, the interrupt request can be cleared by

writing a 0 to this bit. If a 1 is written to this bit, it retains the value it had before the write

The boundary scan register (SDBSR) is a shift register that is placed on the pads to control the

chip's I/O pins. This register can perform a boundary scan test that conforms to the JTAG standard

(IEEE Std 1149.1) using EXTEST, SAMPLE, and PRELOAD commands. Table 21.3 shows the

relationship between the SH7750R's pins and the boundary scan register.

Rev. 6.0, 07/02, page 806 of 986

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