Hitachi SH7750 Hardware Manual page 688

Sh7750 series superh risc engine

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Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data,

Multiprocessor Serial Data Reception: Figure 15.15 shows a sample flowchart for

multiprocessor serial reception.

Use the following procedure for multiprocessor serial data reception after enabling the SCI for

Rev. 6.0, 07/02, page 638 of 986

Data written to SCTDR1

and TDRE flag cleared

to 0 by TXI interrupt

MPBT bit cleared to 0, data

written to SCTDR1, and

TDRE flag cleared to 0 by

TEI interrupt handler

Multiprocessor Bit, One Stop Bit)

TXI interrupt

TEI interrupt

(mark state)

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