Hitachi SH7750 Hardware Manual page 57

Table 1.1 SH7750 Series Features (cont)
Item
Direct memory
access controller
(DMAC)
Timer unit (TMU)
Realtime clock
(RTC)
Serial
communication
interface
(SCI, SCIF)
Features
•
Physical address DMA controller:
 SH7750, SH7750S: 4-channel
 SH7750R: 8-channel
•
Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes
•
Address modes:
 Single address mode
 Dual address mode
•
Transfer requests: External, on-chip module, or auto-requests
•
Bus modes: Cycle-steal or burst mode
•
Supports on-demand data transfer
•
Auto-reload 32-bit timer:
 SH7750, SH7750S: 3-channel
 SH7750R: 5-channel
•
Input capture function
•
Choice of seven counter input clocks
•
On-chip clock and calendar functions
•
Built-in 32 kHz crystal oscillator with maximum 1/256 second resolution
(cycle interrupts)
•
Two full-duplex communication channels (SCI, SCIF)
•
Channel 1 (SCI):
 Choice of asynchronous mode or synchronous mode
 Supports smart card interface
•
Channel 2 (SCIF):
 Supports asynchronous mode
 Separate 16-byte FIFOs provided for transmitter and receiver
Rev. 6.0, 07/02, page 7 of 986