Hitachi SH7750 Hardware Manual page 7

Section
5.6.3 Interrupts
7.3 Instruction Set
8.3 Execution Cycles and
Pipeline Stalling
9.1.1 Types of Power-Down
Modes
9.1.2 Register Configuration
9.1.3 Pin Configuration
9.2.2 Peripheral Module Pin
High Impedance Control
9.2.3 Peripheral Module Pin
Pull-Up Control
9.2.4 Standby Control
Register 2 (STBCR2)
9.2.5 Clock-Stop Register 00
(CLKSTP00) (SH7750R Only)
9.2.6 Clock-Stop Clear
Register 00 (CLKSTPCLR00)
(SH7750R Only)
9.4.1 Transition to Deep
Sleep Mode
9.5.2 Exit from Standby
Mode
9.6.1 Transition to Module
Standby Function
9.6.2 Exit from Module
Standby Function
9.7 Hardware Standby Mode
(SH7750S, SH7750R Only)
Page Item
157 (3) Peripheral Module
Interrupts
186 Table 7.7 Branch Instructions Description added
204 to
206
222 Table 9.1 Status of CPU and
Peripheral Modules in Power-
Down Modes
223 Table 9.2 Power-Down Mode
Registers
223 Table 9.3 Power-Down Mode
Pins
226 Other information
226 Other Information
227 Bit table
227 Bit 6, Bits 1 and 0
228, 229
229
230
232 Exit by Interrupt
234
234
235
Description
Description changed
Description amended
Note changed
Hardware standby
(SH7750S, SH7750R)
added to table,
description amended
Description and Note
added to table
Description added to
Function in table and
amended
Description amended
Added
Bit 6 amended to STHZ
and bit 1 to MSTP6,
note added
Description added
Newly added
Added
Description amended,
Note added
Note added
Text amended
Table description and
note added
Description amended
Note deleted
SH7750R added
Rev. 6.0, 07/02, page vii of I