Figure 22.38 Dram Bus Cycle (Edo Mode, Rcd[1:0] = 00, Anw[2:0] = 000, Tpc[2:0] = 001) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

Hide thumbs Also See for SH7750:

Table of Contents

(SA: IO ← memory)

Notes: IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

DACK set to active-high

(EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001)

Figure 22.38 DRAM Bus Cycle

Rev. 6.0, 07/02, page 901 of 986

Chapters

Table of Contents

Sh7750r Sh7750s