Hitachi SH7750 Hardware Manual page 268

Table 8.3 Execution Cycles (cont)
Functional
Category
No. Instruction
Double- 210 FNEG
precision
211 FSQRT
floating-point
instructions
212 FSUB
213 FTRC
FPU system 214 LDS
control
215 LDS
instructions
216 LDS.L
217 LDS.L
218 STS
219 STS
220 STS.L
221 STS.L
Graphics 222 FMOV
acceleration
223 FMOV
instructions
224 FMOV
225 FMOV
226 FMOV
227 FMOV
228 FMOV
229 FMOV
230 FMOV
231 FIPR
232 FRCHG
233 FSCHG
234 FTRV
Notes: 1. See table 8.1 for the instruction groups.
2. Latency "L1/L2...": Latency corresponding to a write to each register, including
MACH/MACL/FPSCR.
Example: MOV.B @Rm+, Rn "1/2": The latency for Rm is 1 cycle, and the latency for
3. Branch latency: Interval until the branch destination instruction is fetched
Rev. 6.0, 07/02, page 218 of 986
DRn
DRn
DRm,DRn
DRm,FPUL
Rm,FPUL
Rm,FPSCR
@Rm+,FPUL
@Rm+,FPSCR
FPUL,Rn
FPSCR,Rn
FPUL,@-Rn
FPSCR,@-Rn
DRm,XDn
XDm,DRn
XDm,XDn
@Rm,XDn
@Rm+,XDn
@(R0,Rm),XDn
XDm,@Rn
XDm,@-Rm
XDm,@(R0,Rn)
FVm,FVn
XMTRX,FVn
Rn is 2 cycles.
Instruc-
tion Issue
Group Rate
Latency
LS 1 0
FE 1 (23, 24)/
25
FE 1 (7, 8)/9
FE 1 4/5
LS 1 1
CO 1 4
CO 1 1/2
CO 1 1/4
LS 1 3
CO 1 3
CO 1 1/1
CO 1 1/1
LS 1 0
LS 1 0
LS 1 0
LS 1 2
LS 1 1/2
LS 1 2
LS 1 1
LS 1 1/1
LS 1 1
FE 1 4/5
FE 1 1/4
FE 1 1/4
FE 1 (5, 5, 6,
7)/8
Execu- Lock
tion
Pattern Stage Start Cycles
#1 — —
#41 F3 2
F1 21
F1 2
#39 F1 2
#38 F1 2
#1 — —
#32 F1 3
#2 — —
#33 F1 3
#1 — —
#1 — —
#2 — —
#2 — —
#1 — —
#1 — —
#1 — —
#2 — —
#2 — —
#2 — —
#2 — —
#2 — —
#2 — —
#42 F1 3
#36 — —
#36 — —
#43 F0 2
F1 3
—
22
3
2
6
2
—
3
—
3
—
—
—
—
—
—
—
—
—
—
—
—
—
1
—
—
4
4