Rtc Control Register 2 (Rcr2) - Hitachi SH7750 Hardware Manual

Bit 0—Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR,
RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1
matches the respective counter values.
Bit 0: AF
0
1
Note: * Writing 1 does not change the value.
Bits 6, 5, 2, and 1—Reserved. The initial value of these bits is undefined. A write to these bits is
invalid, but the write value should always be 0.

11.2.16 RTC Control Register 2 (RCR2)

RCR2 is an 8-bit readable/writable register used for periodic interrupt control, 30-second
adjustment, and frequency divider RESET and RTC count control.
RCR2 is basically initialized to H'09 by a power-on reset, except that the value of the PEF bit is
undefined. In a manual reset, bits other than RTCEN and START are initialized, while the value
of the PEF bit is undefined. In standby mode RCR2 is not initialized, and retains its current value.
Bit:
Initial value:
Undefined
R/W:
Description
Alarm registers and counter values do not match
[Clearing condition]
When 0 is written to AF
Alarm registers and counter values match*
[Setting condition]
When alarm registers in which the ENB bit is set to 1 and counter values
match*
7 6
PEF PES2 PES1
0
R/W R/W R/W
5 4 3
PES0 RTCEN
0 0 1
R/W R/W
(Initial value)
2 1
ADJ RESET
0 0
R/W R/W
Rev. 6.0, 07/02, page 281 of 986
0
START
1
R/W