Burst (Rcd[1:0] = 01, Cas Latency = 3, Tpc[2:0] = 011); Figure 22.25 Synchronous Dram Normal Read Bus Cycle: Act + Read Commands, Burst (Rcd[1:0] = 01, Cas Latency = 3) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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(SA: IO ← memory)

Notes: IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

DACK set to active-high

Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands,

Burst (RCD[1:0] = 01, CAS Latency = 3)

Rev. 6.0, 07/02, page 887 of 986

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