Figure 22.15 Sram Bus Cycle: Basic Bus Cycle (No Wait) - Hitachi SH7750 Hardware Manual

Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high

Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait)

T1
CKIO
t
AD
A25 – A0
t
CSD
t
RWD
RD/
t
RSD
D63 – D0
(read)
t
WED1
t
WDD
D63 – D0
(write)
t
BSD
t
DACD
DACKn
(SA: IO ← memory)
t
DACDF
DACKn
(SA: IO → memory)
t
DACD
DACKn
(DA)
T2
t
AD
t
CSD
t
RWD
t t
RSD RSD
t t
RDS RDH
t t
WEDF WEDF
t t
WDD WDD
t
BSD
t t
DACD DACD
t
DACDF
t
DACD
Rev. 6.0, 07/02, page 877 of 986