Hitachi SH7750 Hardware Manual page 475

Tpr
CKIO
Bank
Precharge-sel
Address
RD/
DQMn
D63–D0
(read)
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses)
Tpc Tr Trw Tc1
Row
Row
Row
Tc2 Tc3 Tc4/Td1 Td2
H/L
c1
c1
Rev. 6.0, 07/02, page 425 of 986
Td3 Td4
c2 c3 c4