Insertion, Ans = 1, Anh = 1) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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(SA: IO ← memory)

(SA: IO → memory)

Notes: IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

DACK set to active-high

* SH7750R only

Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time

Rev. 6.0, 07/02, page 880 of 986

Insertion, AnS = 1, AnH = 1)

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Sh7750r Sh7750s