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Figure 13.61
MPX Interface Timing 5
(Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits,
Transfer Data Size: 32 Bytes) .......................................................................... 461
Figure 13.62
MPX Interface Timing 6
(Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits,
Transfer Data Size: 32 Bytes) .......................................................................... 462
Figure 13.63
MPX Interface Timing 7
(Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits,
Transfer Data Size: 32 Bytes) .......................................................................... 463
Figure 13.64
MPX Interface Timing 8
(Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 64 Bits,
Transfer Data Size: 32 Bytes) .......................................................................... 464
Figure 13.65
MPX Interface Timing 1
(Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 64 Bytes) .......................................................................... 465
Figure 13.66
MPX Interface Timing 2
(Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bytes) .......................................................................... 466
Figure 13.67
MPX Interface Timing 3
(Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 64 Bytes) .......................................................................... 467
Figure 13.68
MPX Interface Timing 4
(Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bytes) .......................................................................... 468
Figure 13.69
MPX Interface Timing 5
(Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) .......................................................................... 469
Figure 13.70
MPX Interface Timing 6
(Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) .......................................................................... 470
Figure 13.71
MPX Interface Timing 7
(Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) .......................................................................... 471
Figure 13.72
MPX Interface Timing 8
(Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) .......................................................................... 472
Figure 13.73
Example of 64-Bit Data Width Byte Control SRAM....................................... 474
Figure 13.74
Byte Control SRAM Basic Read Cycle (No Wait) .......................................... 475
Figure 13.75
Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)................. 476
Figure 13.76
Byte Control SRAM Basic Read Cycle
(One Internal Wait + One External Wait) ........................................................ 477
Figure 13.77
Waits between Access Cycles.......................................................................... 479
Figure 13.78
Arbitration Sequence ....................................................................................... 482
Rev. 6.0, 07/02, page xxxviii of I
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