Dma Operation Register (Dmaor) - Hitachi SH7750 Hardware Manual

14.2.5

DMA Operation Register (DMAOR)

Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Note: The AE and NMIF bits can only be written with 0 after being read as 1, to clear the flags.
The COD bit can be written to in the SH7750S only.
DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode.
DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in
standby mode and deep sleep mode.
Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode.
Bit 15: DDT
0
1
Note: BAVL (DRAK0) is an active-high output in normal DMA mode. When the DDT bit is set to 1,
the BAVL pin function is enabled and this pin becomes an active-low output.
31 30 29
— —
0 0
R R
23 22 21
— —
0 0
R R
15 14 13
DDT —
0 0
R/W R
7 6
— —
0 0
R R
Description
Normal DMA mode
On-demand data transfer mode
28 27
— — —
0 0 0
R R R
20 19
— — —
0 0 0
R R R
12 11
— — —
0 0 0
R R R
5 4 3
— COD —
0 0 0
R R/(W) R
26 25
— —
0 0
R R
18 17
— —
0 0
R R
10 9
— PR1
0 0
R R/W
2 1
AE NMIF
0 0
R/(W) R/(W)
(Initial value)
Rev. 6.0, 07/02, page 507 of 986
24
—
0
R
16
—
0
R
8
PR0
0
R/W
0
DME
0
R/W