TRWL[2:0] = 010)........................................................................................... 893
TPC[2:0] = 001)............................................................................................... 901
TPC[2:0] = 001)............................................................................................... 902
TPC[2:0] = 001)............................................................................................... 903
Figure 22.41
DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001,
Figure 22.48
DRAM Burst Bus Cycle: RAS Down Mode Continuation
Rev. 6.0, 07/02, page xliv of I