Pin Configuration; Table 13.1 Bsc Pins - Hitachi SH7750 Hardware Manual

13.1.3

Pin Configuration

Table 13.1 shows the BSC pin configuration.

Table 13.1 BSC Pins

Name Signals
Address bus A25–A0
Data bus D63–D52,
D31–D0
Data bus/port D51–D32/
PORT19–
PORT0
BS
Bus cycle start
CS6–CS0
Chip select 6–0
Read/write RD/WR
RAS
Row address
strobe
RD/CASS/
Read/column
FRAME
address strobe/
cycle frame
WE0/CAS0/
Data enable 0
DQM0
Rev. 6.0, 07/02, page 314 of 986
I/O Description
O Address output
I/O Data input/output
When port functions are used and DDT mode is
selected, input the DTR format. Otherwise, when
port functions are used, D60-D52 cannot be used
and should be left open.
I/O When port functions are not used: data input/output
When port functions are used: input/output port
(input or output set for each bit by register)
O Signal that indicates the start of a bus cycle
When setting synchronous DRAM interface:
asserted once for a burst transfer
For other burst transfers: asserted each data cycle
O Chip select signals that indicate the area being
accessed
CS5 and CS6 are also used as PCMCIA CE1A and
CE1B
O Data bus input/output direction designation signal
Also used as the DRAM/synchronous
DRAM/PCMCIA interface write designation signal
RAS signal when setting DRAM/synchronous DRAM
O
interface
O Strobe signal that indicates a read cycle
When setting synchronous DRAM interface: CAS
signal
When setting MPX interface: FRAME signal
O When setting synchronous DRAM interface:
selection signal for D7–D0
When setting DRAM interface: CAS signal for
D7–D0
When setting MPX interface: high-level output
In other cases: write strobe signal for D7–D0