Mitsubishi Electric MELSEC-Q Series User Manual page 101

(3) Differences from link refresh
Item
Number of steps
Processing speed (LD B0
Data reliability
(Note-1): The given value is for the Q06UDEHCPU.
(Note-2): When "Block Data Assurance per Station" is enabled (Refer to Section 8.3.4.)
(Note-3): When the conditions for the secured 32-bit data are satisfied (Refer to Section 8.3.4.)
(4) Shortening the link refresh time and transmission delay time
(a) Shortening the link refresh time
Remove infrequently used link devices from the link refresh range, and directly
read or write the corresponding data using link direct devices. This reduces the
number of the link refresh points to the CPU module, resulting in a shorter link
refresh time. (Refer to Section 8.3.2.)
(b) Shortening the transmission delay time
Because the link direct device allows direct reading or writing of data to the link
devices of the Simple Motion module at the time of the instruction execution, the
transmission delay time can be shortened.
REMARK
Link refresh is executed in END processing of the sequence scan of the CPU
module.
(5) Precautions
For cyclic data assurance of more than 32 bits, refer to Section 8.3.4.
Link refresh
1 step
(Note-1)
)
High speed (0.0095µs)
Station-based or 32-bit units
(Note-3)
8 - 11
Chapter 8 FUNCTIONS
Access method
Direct access
2 steps
Low speed (10 to 100µs)
(Note-2)
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