Jpds I/O Characteristics; Diagnostic Features - GE Mark VIeS System Manual

10.8.2 JPDS I/O Characteristics

• Three power supply inputs are provided on JR, JS, and JT. The connector uses pins 8 and 9 for positive 28 V power. Pins
1-3 are used for 28 return, providing 24 A steady state capacity. These connectors include low level signals capable of
detecting status switches on each supply and generating a feedback signal to the PPDA. Pin 4 provides positive 10 V
wetting to the switch, and the return is on pin 5. Pins 6 and 7 are not connected.
• Terminal boards TB1 and TB2 at the bottom and top of the board provide access to the three power buses. If two adjacent
JPDS boards are used, jumpers may be placed between TB1 and TB2 on the boards to parallel the bus on the two boards.
For a single power bus fed by redundant supplies, jumpers may be placed between PR, PS, and PT terminals to tie the
positive bus terminals together.
Attention
• Three two-pin Mate-N-Lok connectors (JCR, JCS, and JCT) are provided to power the controllers or other loads. Pin 1 is
28 V, and pin 2 is the return.
• Three two-pin Mate-N-Lok connectors (JAR, JAS, and JAT) with filtering and fusing are provided for auxiliary loads.
These outputs feature a series common mode filter inductor, and they have self-resetting polysilicon fuses rated for 1.6 A
at 20 °C, derated to 0.8 A at 70 °C. Pin 1 is 28 V, and pin 2 is the return.
• Six Mate-N-Lok connectors with six pins each are provided to supply R, S, and T power to remote JPDP or JPDH
boards, or directly to JPDL boards when used with the appropriate wire harness. On all six connectors, pins 1-3 are 28 V
return, pin 4 is 28 R, pin 5 is 28 S, and pin 6 is 28 T.
• The DC62 connector JA1 is used for a PPDA power diagnostic I/O pack. It contains the status feedback signals for up to
six core power distribution boards.
• P4 supplies power to the PPDA I/O pack. It is a power circuit formed from R, S, and T power using a Diode-OR
arrangement followed by a polysilicon self-resetting fuse rated for the PPDA power requirements. This ensures that the
I/O pack receives power if any of the three power buses are active.
• Diagnostic daisy chain 50 pin ribbon cable connectors P1 and P2 are located on top and bottom of the board. They are
used for pass-through of the diagnostic signals.

10.8.2.1 Diagnostic Features

JPDS have feedback wiring that is different from the other core PDM boards. One JPDS will host the PPDA I/O pack on the
JA1 connector. On that board, the P1 connector is not used because the output signals are sent to the PPDA. If a second JPDS
board is used, the P1 connector on the second board will be used to conduct its feedback into P2 of the board hosting PPDA.
In either case, the P2 connector provides passage of feedback signals from other core PDM boards. The following signals are
created by JPDS:
• An electronic ID identifies the board type, revision, and serial number.
• PS28vStat_R, _S, _T are three analog P28 voltage readings for R, S, and T bus. Separate analog feedback signals are
used. Accuracy is specified to be ±1% of full scale and calculated accuracy is ±0.2% at 3 sigma.
• One dry contact from each of the three power supplies (DryCntStat_R, _S, _T) yields three Boolean values.
• Three Aux output fuse status signals (AuxFuseStat_R, _S, _T) multiplexed into a single analog value yields three
Boolean values after PPDA decodes the signal.
JPDS provides the following four test point outputs for connection of external test equipment:
• HWI - 28PR
• HW2 - 28PS
• HW3 - 28PT
• HW4 - 28N
The positive side test points include series 10 kΩ current limiting resistors. These allow access to all three 28 V power buses
and the common return circuit.
PDM Power Distribution Modules
Do not exceed the maximum available fault current out of the JPDS board when tying
the positive bus terminals together. For applications requiring greater available fault
current, the JPDM is a better choice.
Public Information
GEH-6855_Vol_II System Guide 389