GE Mark VIeS System Manual page 187

• mA outputs connect the DAC to the external actuator with the return path passed to ground. Confirmation of the current
is received by the PGA sensing the voltage drop on a series resistor at the DAC output. If the HART option is enabled,
the DAC may be modulated with an AC tone to communicate to the external actuator with the response sensed by
connecting a bandpass filter and A/D to the output terminal.
• Digital inputs are similar to the ma input settings, with specific paths set by the options:
− Externally-fed switch inputs are connected to IO+ and then to a 12.5K input load to ground. The PGA has a 20 V
limit so a series resistor is added for higher field supplies to avoid false error alarms for excess input voltage.
− Externally-fed switches with line monitoring (open/short detection) use two external resistors in series with and
parallel to the external switch. This connects to the 12.5K input load with the PGA/ADC path used to check for
voltages in correct ranges. If too high or too low the external wiring is declared to be faulty.
− Internally-fed switches use the DAC to drive a current through the external switch and back through the mA burden
resistor to ground. For a simple switch input, the DAC is set for 10 mA flow. By sensing the burden resistor voltage,
the switch state is determined. An option for line monitoring (open/short detection) with two resistors allows for
fault checking, where the DAC is set for 5 V to allow for the current to change.
− NAMUR style sensors use a device connected to the YUAA set for 8.2 V output with a 1K series resistance. By
sensing the terminal voltage, the amount of current flow is derived and in turn the external device state is determined
as on, off, or faulty.
All of the settings are provided through complex programmable logic device (CPLD) controlling groups of four channels,
supporting commands to the switch block settings, dataflow to the DAC for output settings, dataflow from the PGA and
HART ADC channels (one for low bandwidth signals covering DC to 20 Hz, and a second for bandpass energy on HART
signaling), first stage of decimation and filtering, HART modulation output using a delta sigma bit output feeding a hardware
low pass filter, and data transfers with the YUAA's processor board's FPGA. The processor and FPGA provide a second level
of filtering and decimation down to the frame rate along with completion of the HART demodulation and UART functions.
YUAA Universal I/O Modules
Public Information
GEH-6855_Vol_II System Guide 187