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S3F84B8_UM_REV 1.00
8.2.2 HARDWARE RESET VALUES
shows the reset values of the CPU and system registers, peripheral control registers, and peripheral
Figure 8-1
data registers, following a reset operation.
Following notation is used to represent the reset values:
A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
An "x" means that the bit value is undefined after a reset.
A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value.
Register Name
Locations D0-D2H are not mapped
Basic timer control register
Clock control register
System flags register
Register Pointer 0
Register Pointer 1
Location D8H is not mapped
Stack Pointer register
Instruction Pointer (High Byte)
Instruction Pointer (Low Byte)
Interrupt Request register
Interrupt Mask Register
System Mode Register
Register Page Pointer
Port 0 data register
Port 1 data register
Port 2 data register
Port 0 interrupt control register
Port 0 control register (High byte)
Port 0 control register (Low byte)
Port 0 interrupt pending register
Port 1 control register (Low byte)
Port 2 control register (High byte)
Port 2 control register (Low byte)
Comparator 0 control register
Comparator 1 control register
Table 8-1
S3F84B8 Set1 Registers Values after RESET
Mnemonic
BTCON
CLKCON
FLAGS
RP0
RP1
SPL
IPH
IPL
IRQ
IMR
SYM
PP
P0
P1
P2
P0INT
P0CONH
P0CONL
P0PND
P1CON
P2CONH
P2CONL
CMP0CON
CMP1CON
Address and
Location
Address
R/W
D3H
R/W
D4H
R/W
D5H
R/W
D6H
R/W
D7H
R/W
D9H
R/W
DAH
R/W
DBH
R/W
DCH
R
DDH
R/W
DEH
R/W
DFH
R/W
E0H
R/W
E1H
R/W
E2H
R/W
E3H
R/W
E4H
R/W
E5H
R/W
E6H
R/W
E7H
R/W
E8H
R/W
E9H
R/W
EAH
R/W
EBH
R/W
8-6
8 RESET AND POWER-DOWN
RESET Value (Bit)
7
6
5
4
3
2
0
0
0
0
0
0
0
–
–
0
0
–
x
x
x
x
x
x
1
1
0
0
0
–
1
1
0
0
1
–
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
x
x
x
x
x
x
0
–
–
x
x
x
0
0
0
0
0
0
–
0
0
0
0
0
–
–
–
–
–
0
0
0
0
0
0
0
–
0
0
0
0
–
–
–
0
0
0
0
0
0
–
–
0
0
–
0
0
0
0
–
–
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
–
–
0
0
0
0
0
0
0
0
0
1
0
0
0
–
–
0
0
–
–
–
–
x
x
x
x
x
x
0
0
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
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