Conversion Timing - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

13.1.3 CONVERSION TIMING

The A/D conversion process requires four steps (4 clock edges) to convert each bit and 10 clocks to step up A/D
conversion. Therefore, a total of 50 clocks are required to complete a 10-bit conversion. If 8MHz CPU clock
frequency is used, one clock cycle is 500ns (4/fxx). If each bit conversion requires 4 clocks, the conversion rate is
calculated as follows:
4 clocks/bit  10-bits + step-up time (10 clock) = 50 clocks
50 clocks  500ns = 25s at 8MHz, 1 clock time = 4/fxx (assuming ADCON.2–.1 = 01)
13.1.4 INTERNAL A/D CONVERSION PROCEDURE
1. Analog input must remain between the voltage range of V
2. Configure the analog input pins to input mode by setting the P2CONH and P2CONL registers.
3. Before the conversion operation starts, you must select one of the eight input pins (ADC0-ADC7) by writing
the appropriate value to the ADCON register.
4. When conversion is complete (that is 50 clocks have elapsed), the Interrupt pending bit (EOC flag) is set to
"1". If ADC interrupt is enabled, a request will be sent to the CPU or EOC check can be made to verify that the
conversion was successful.
5. The converted digital value is loaded to the output register, ADDATAH (8-bit) and ADDATAL (2-bit). The ADC
module then enters an Idle state.
6. The digital conversion result can now be read from ADDATAH and ADDATAL registers.
Analog
Input Pin
Figure 13-5
V
DD
101
Recommended A/D Converter Circuit for Highest Absolute Accuracy
and V
SS DD.
X
ADC0-ADC7
X
OUT
S3F84B8
V
SS
13-5
13 A/D CONVERTER
IN