Figure 14-2 Cmp Interrupt Mode Control Register (Cmpint) - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
MSB
CMP 0 output polarity select bit
0 = CMP0 output is not inverted
1 = CMP0 output is inverted
NOTE: Please refer to the programming tip for proper configuration sequence.
CMP3 Interrupt mode select bit
00 = invalid
01 = falling edge interrupt
10 = rising edge interrupt
11 = falling and rising edge interrupt
CMP0 Control Register (CMP0CON)
EAH, Set1, Bank0, Reset = 02H, R/W
.7 .6 .5 .4
Not used
CMP0 enable bit
0 = Disable comparator
1 = Enable comparator
Figure 14-1
CMP Interrupt Mode Control Register (CMPINT)
EEH, Set1, Bank0, Reset = FFH, R/W
MSB .7 .6 .5
CMP2 Interrupt mode select bit
00 = invalid
01 = falling edge interrupt
10 = rising edge interrupt
11 = falling and rising edge interrupt
Figure 14-2 CMP Interrupt Mode Control Register (CMPINT)
.3 .2 .1 .0
CMP0 interrupt pending bit:
0 = No interrupt pending
(Clear pending bit when write)
1
= Interrupt is pending
CMP0 status bit
0 = CMP0_N > CMP0_P
1 = CMP0_N < CMP0_P
CMP0 Interrupt enable bit
0 = Disable interrupt
1 = Enable interrupt
CMP0 Control Register (CMP0CON)
.4 .3 .2 .1
CMP1 Interrupt mode select bit
00 = invalid
01 = falling edge interrupt
10 = rising edge interrupt
11 = falling and rising edge interrupt
14-2
LSB
.0 LSB
CMP0 Interrupt mode select bit
00 = invalid
01 = falling edge interrupt
10 = rising edge interrupt
11 = falling and rising edge interrupt
14 COMPARATOR