S3F84B8 Interrupt Structure - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

5.1.5 S3F84B8 INTERRUPT STRUCTURE

The S3F84B8 microcontroller supports 17 interrupt sources. Every interrupt source has a corresponding interrupt
address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in
Figure 5-2.
When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which
contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt
with lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single
level are fixed in the hardware).
When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled, and the
program counter value and status flags are pushed to stack. The starting address of service routine is fetched
from the appropriate vector address (plus the next 8-bit value to concatenate full 16-bit address) and the service
routine is executed.
Levels
RESET
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
NOTE: Within a given interrupt level, the low vector address has high priority.
Vectors
100H
D0H
D2H
D4H
D6H
D8H
DAH
DCH
DEH
E0H
E2H
E4H
E6H
E8H
EAH
ECH
EEH
F0H
For example, D0H has higher priority than D2H within the level IRQ0. The priorities
within each level are set at the factory.
Figure 5-2
Sources
Basic timer overflow
Timer A overflow
Timer A match/capture
CMP3 Interrupt
CMP2 Interrupt
CMP1 Interrupt
CMP0 Interrupt
Timer D overflow
Timer D match
Timer C match
PWM Counter Overflow
P0.0 external interrupt(INT0)
P0.1 external interrupt(INT1)
P0.3 external interrupt(INT2)
P0.4 external interrupt(INT3)
P0.5 external interrupt(INT4) S/W
P0.6 external interrupt(INT5) S/W
ADC Interrupt
S3F84B8 Interrupt Structure
5-3
5 INTERRUPT STRUCTURE
Reset/Clear
H/W
H/W,S/W
S/W
S/W
S/W
S/W
S/W
H/W,S/W
S/W
S/W
H/W, S/W
S/W
S/W
S/W
S/W
S/W