Indexed (X) Addressing Mode - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

3.7 INDEXED (X) ADDRESSING MODE

Indexed (X) addressing mode adds an offset value to base address while executing an instruction in order to
calculate the effective operand address (see
locations in the internal register file or external memory. Note that you cannot access locations C0H–FFH in set 1
using Indexed addressing mode.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range -128 to
+127. This applies to external memory accesses only (see
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in a working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address
(see
Figure 3-9).
The only instruction that supports Indexed addressing mode for internal register file is the Load instruction (LD).
The LDC and LDE instructions support Indexed addressing mode for internal program memory and external data
memory, when implemented.
Two-Operand
Instruction
Example
Sample Instruction:
LD
Figure
Program Memory
Base Address
dst/src x
Point to One of the
OPCODE
Woking Register
R0, #BASE[R1] ; Where BASE is an 8-bit immediate value
Figure 3-7 Indexed Addressing to Register File
3-7). You can use Indexed addressing mode to access
Figure 3-8).
Register File
RP0 or RP1
~
Value used in
Instruction
OPERAND
+
~
3 LSBs
(1 of 8)
3-7
3 ADDRESSING MODES
~
Selected RP
points to
start of
working
register
block
~
INDEX