Tm — Test Under Mask - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
6.3.71 TM — TEST UNDER MASK
dst,src
TM
dst AND src
Operation:
This instruction tests selected bits in destination operand for logic zero value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of source operand (mask),
which is ANDed with destination operand. The zero (Z) flag can then be checked to determine the
result. The destination and source operands remain unaffected.
C: Unaffected.
Flags:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
opc
opc
opc
Given R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register
Examples:
02H = 23H:
TM
TM
TM
TM
TM
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
contains the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination
register for a "0" value. Since the mask value does not match the test bit, the Z flag is cleared to
logic zero and can be tested to determine the result of TM operation.
dst | src
src dst
dst src
R0,R1
R0,@R1
00H,01H
00H,@01H
00H,#54H
Bytes
2
3
3
R0 = 0C7H, R1 = 02H, Z = "0"
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "0"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "0"
Register 00H = 2BH, Z = "1"
6-83
6 INSTRUCTION SET
Cycles Opcode
(Hex)
4 72
6 73
6 74
6 75
6 76
Addr Mode
dst src
r r
r lr
R R
R IR
R IM