Amtdata — Anti-Mis-Trigger Data Register: F6H, Bank0 - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
4.1.2 AMTDATA — ANTI-MIS-TRIGGER DATA REGISTER: F6H, BANK0
Bit Identifier
RESET Value
Read/Write
Addressing Mode
.7–.0
NOTE: 0 < TST (setting time) < 4/fpwmclk
4.1.3 BTCON — BASIC TIMER CONTROL REGISTER: D3H, BANK0
Bit Identifier
RESET Value
Read/Write
.7–.4
.3–.2
.1
.0
NOTE: When you write a "1" to BTCON.0 (or BTCON.1), the basic timer divider (or basic timer counter) is cleared. The bit is
then automatically cleared to "0".
.7 .6
0 0
R/W R/W
Register addressing mode only
Anti-mis-trigger time= (AMTDATA  4)/fpwmclk + TST
.7 .6
0 0
R/W R/W
Watchdog Timer Function Enable Bit
1 0 1 0 Disables watchdog timer function.
Others Enables watchdog timer function.
Basic Timer Input Clock Selection Code
f /4096
0 0
OSC
f /1024
0 1
OSC
f /128
1 0
OSC
1 1 Invalid setting
Basic Timer 8-Bit Counter Clear Bit
0 No effect.
1 Clears the basic timer counter value.
Basic Timer Divider Clear Bit
0 No effect.
1 Clears both the dividers.
.5 .4
0 0
R/W R/W R/W
.5 .4
0 0
R/W R/W R/W
4-6
4 CONTROL REGISTERS
.3 .2 .1
0 0 0
R/W R/W
.3 .2 .1
0 0 0
R/W R/W
.0
0
R/W
.0
0
R/W