Samsung S3F84B8 User Manual page 265

S3F84B8_UM_REV 1.00
14.1.1.2.2 Block Diagram of Comparator 1/2/3
CMP1/2/3CON.7-.5
0.45 VDD
0.50 VDD
MUX
...
0.80 VDD
CMP0_N
C1/2/3PLR (CMP1/2/3CON.4)
NOTE:
1. Polarity selection bit (CMP1/2/3CON.4) will not affect interrupt generation logic .
2. PWM lock signal is falling edge active only .


DI
LD
AND
LD
EI


C1/2/3EN (CMP1/2/3CON.3)
+
CMP1/2/3
-
Figure 14-8
Example 14-1
CMPINT, #055H
CMP0/1/2/3CON, #0FEH
CMP0/1/2/3CON, #0CH
INT Enable (CMP1/2/3CON.2)
SET
CMP1/2/3CON.0
D
Q
Fosc
Q
CLR
CMP1/2/3CON.1
Block Diagram of Comparator 1/2/3
Comparator Configuration
; Falling edge interrupt
; Must clear the pending bit before enabling CMP
; Enables CMP, enables interrupt
14-7
14 COMPARATOR
INT
CTRL
CMPINT.3-.2/.5-.4/.7-.6
PWM
Interrupt