Samsung S3F84B8 User Manual page 247

S3F84B8_UM_REV 1.00
TCCON and TDCON are located in address E5H and E9H, Set1 Bank1, and are read/write addressable using
register addressing mode.
A reset clears TCCON to "00H". This disables the Timer C interrupt. You can clear the Timer C counter at any
time during normal operation by writing a "1" to TCCON.5.
A reset clears TDCON to "00H". This sets the Timer D to work in interval Timer mode, and disables the Timer D
interrupt. You can clear the Timer D counter at any time during normal operation by writing a "1" to TDCON.5.
To enable the Timer C interrupt (TCINT) and Timer D interrupt (TDINT), you must write TCCON.7 to "0" and
TCCON.3 (TDCON.3) to "1". To generate the exact time interval, you should write TCCON.5 (TDCON.5) and
TCCON.1 (TDCON.1), which clears the counter and interrupt pending bit.
To detect an interrupt pending condition when TCINT and TDINT are disabled, the application program can poll
for the pending bit, TCCON.1 and TDCON.1. When a "1" is detected, a Timer C interrupt (TCINT) or Timer D
interrupt (TDINT) is pending. When the TCINT and TDINT sub-routines have been serviced, the pending
condition must be cleared by the software by writing a "0" to the Timers C and D interrupt pending bit, TCCON.1
and TDCON.1, respectively.
Also, to enable the Timer D overflow interrupt (TDOVF), you must write TCCON.7 to "0" and TDCON.2 to "1".
To generate the exact time interval, you should write TDCON.5 and TDCON.1, which clears the counter and
interrupt pending bit.
Timer 0 operation mode selection bit
0 = Two 8-bit timers mode (Timer C/D)
1 = One 16-bit timer mode (Timer 0)
Timer C Control Register (TCCON)
E5H, Set1, Bank1, Reset = 00H, R/W
MSB .7 .6
Not used
Timer C counter clear bit:
0 = No effect
1 = Clear Timer A counter
(after clearing, return to zero)
Timer C start/stop bit:
0 = Stop Timer C
1 = Start Timer C
Figure 12-4
.5 .4 .3 .2
Not used
Timer C Match interrupt enable bit:
0 = Disable Interupt
1 = Enable interrupt
Timer C Control Register (TCCON)
12-6
.1 .0 LSB
Not used
Timer C Match interrupt pending bit:
0 = No interrupt pending
(clear pending bit when write)
12 TIMER 0