Imr — Interrupt Mask Register: Ddh, Bank0 - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
4.1.16 IMR — INTERRUPT MASK REGISTER: DDH, BANK0
Bit Identifier
Reset Value
Read/Write
.7
.6
.5
.4
.3
.2
.1
.0
NOTE: When an interrupt level is masked, the CPU does not recognize any interrupt requests that are issued.
.7 .6
x x
R/W R/W
Interrupt Level 7 (IRQ7)
0 Disables (mask).
1 Enables (unmask).
Interrupt Level 6 (IRQ6)
0 Disables (mask).
1 Enables (unmask).
Interrupt Level 5 (IRQ5)
0 Disables (mask).
1 Enables (unmask).
Interrupt Level 4 (IRQ4)
0 Disables (mask).
1 Enables (unmask).
Interrupt Level 3 (IRQ3)
0 Disables (mask).
1 Enables (unmask).
Interrupt Level 2 (IRQ2)
0 Disables (mask).
1 Enables (unmask).
Interrupt Level 1 (IRQ1)
0 Disables (mask).
1 Enables (unmask).
Interrupt Level 0 (IRQ0)
0 Disables (mask).
1 Enables (unmask).
.5 .4
x x
R/W R/W R/W
4-17
4 CONTROL REGISTERS
.3 .2 .1
x x x
R/W R/W
.0
x
R/W