Clock Status During Power-Down Modes - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

7.1.1 CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop and Idle, affect clock oscillation as follows:

In Stop mode, the main oscillator "freezes". This in turn halts the CPU and peripherals. The contents of
register file and current system register values are retained. Using a reset operation or an external interrupt
with RC-delay noise filter (for S3F84B8, INT0–INT5), the Stop mode is released and oscillation is started.

In Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt control and timer. The
current CPU status is retained, including stack pointer, program counter, and flags. Data in the register file is
retained. Using a reset or an interrupt (external or internally-generated), the Idle mode is released.
7.1.2 SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the
following functions:

Enables/disables the oscillator IRQ wake-up function (CLKCON.7).

Divides oscillator frequency by value: non-divided, 2, 8, or 16 (CLKCON.4 and CLKCON.3)
The CLKCON register controls whether an external interrupt can be used to trigger a Stop mode release. (This
function is known as "IRQ wake-up".) The IRQ wake-up enable bit is CLKCON.7.
After a reset, the external interrupt oscillator wake-up function is enabled, and f
selected as the CPU clock. If necessary, you can increase the CPU clock speed to f
Oscillator IRQ wake-up enable bit:
0 = Enable IRQ for main system
oscillator wake-up function in
power down mode.
1 = Disable IRQ for main system
oscillator wake-up function in
power down mode.
System Clock Control Register (CLKCON)
MSB .7 .6 .5
Not used for S3F84B8
Figure 7-3 System Clock Control Register (CLKCON)
D4H, R/W
.4 .3 .2
Not used for S3F84B8
Divide-by selection bits for
CPU clock frequency:
00 = fosc/16
01 = fosc/8
10 = fosc/2
11 = fosc (non-divided)
7-2
7 CLOCK CIRCUIT
/16 (slowest clock speed) is
OSC
, f /2 or f
OSC OSC
.1 .0 LSB
/8.
OSC