Interrupt Mask Register (Imr) - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

5.1.10 INTERRUPT MASK REGISTER (IMR)

The interrupt mask register, IMR (DDH, Set1) is used to enable or disable interrupt processing for individual
interrupt levels. After a reset, all IMR bit values are undetermined and must be written to their required settings by
the initialization routine.
Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of
an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's
IMR bit to "1", interrupt processing for the level is enabled (not masked).
The IMR register is mapped to register location DDH, Set1. Bit values can be read and written by instructions
using the Register addressing mode.
MSB
Interrupt Mask Register (IMR)
DDH, Set1, R/W
.7 .6 .5
IRQ5
IRQ6
IRQ7
Before IMR register is changed to any value,
NOTE:
all interrupts must be disable.
Using DI instruction is recommended.
Figure 5-6
.4 .3 .2
IRQ2
IRQ3
IRQ4
Interrupt level enable bit:
0 = Disable (mask) interrupt level
1 = Enable (un-mask) interrupt level
Interrupt Mask Register (IMR)
5-9
5 INTERRUPT STRUCTURE
.1 .0 LSB
IRQ0
IRQ1