Interrupt Structure - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

5 INTERRUPT STRUCTURE

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INTERRUPT STRUCTURE
5.1 OVERVIEW OF INTERRUPT STRUCTURE
The interrupt structure in S3C8/S3F8 series has three basic components: levels, vectors, and sources. The
SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific
interrupt level has more than one vector address, the vector priorities are established in hardware. A vector
address can be assigned to one or more sources.
5.1.1 LEVELS
Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks
can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight
possible interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an
interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from
device to device. The S3F84B8 interrupt structure recognizes eight interrupt levels.
The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just
identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is
determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR
settings allow you to define complex priority relationships between different levels.
5.1.2 VECTORS
Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The
maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for
S3C8/S3F8 series devices is always much smaller). If an interrupt level has more than one vector address, the
vector priorities are set in hardware. S3F84B8 uses 17 vectors.
5.1.3 SOURCES
A source refers to any peripheral that generates an interrupt. It can be an external pin or a counter overflow. Each
vector can have several interrupt sources. There are 17 possible interrupt sources in S3F84B8 interrupt structure,
which means that every source can have its own vector.
When a service routine starts, the respective pending bit should be either cleared automatically by the hardware
or cleared manually by the software. The characteristics of source's pending mechanism determine which method
should be used to clear its respective pending bit.
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