Pwm Functional Description - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM

16.2.3 PWM FUNCTIONAL DESCRIPTION

By disabling the linkage of CMPs and PWM (setting PWMCCON to '00H'), PWM module can work in normal 10-bit
mode. PWM output will toggle either on PWM counter match or overflow. The output level can be set as inverted
(PWMCON.5 = 1) or non-inverted (PWMCON.5 = 0).
In comparator-cooperation mode, if linkage is enabled (PWMCCON.6/4/2/0 = 1), the PWM will work according to
the outputs of four comparators. If all the comparators do not generate valid trigger signals, the PWM will work as
normal 10-bit PWM.
For comparator0, the output falling edge will clear PWM counter. It will restart one PWM cycle immediately
(maximum delay = 4/fPWM) or after some programmable delay period (known as delay trigger function; enabled
when PWMCCON.0 = 1). The delay period is programmable through PWMDL register.
Anti-mis-trigger function can be used to prevent the PWM from being triggered by unwanted noise. There is an
internal timer used to realize PWM anti-mis-trigger function. When the PWM starts a new cycle, the internal timer
will reset and start to up count at PWM clock. Before match happens, signals from Comparator 0 will be
neglected. Thus, they will not trigger PWM to start another new cycle.
For comparator1, 2, and 3, the output falling edge will either directly stop the PWM (hard lock), or stop the current
PWM cycle and restart PWM when the next cycle begins with a preset PWM data called PWMPDATA (soft lock).
To avoid invalid trigger or lock, register PWMCCON must be set to appropriate value before enabling PWM
module.
You can select a clock for the PWM counter by setting PWMCON.6–.7. Clocks that you can select are f /64,
OSC
f /8, f /2, f /1.
OSC OSC OSC
16-3