Clock Status During Power-Down Modes; System Clock Circuit Diagram - Samsung S3C8275X User Manual

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:
•
In stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset
operation or an external interrupt (with RC delay noise filter).
•
In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers and timer/
counters. Idle mode is released by a reset or by an external or internal interrupt.
INT
Main-System
Oscillator
Circuit
Stop
OSCCON.3
OSCCON.0
STOP OSC
inst.
STPCON
CLKCON.4-.3
Stop Release
f
x
Selector 1
f
XX
1/1-1/4096
Frequency
Dividing
Circuit
1/1 1/2 1/8
Selector 2
Figure 7-6. System Clock Circuit Diagram
Sub-system
f
xt
Oscillator
Circuit
Basic Timer
Timer/Counters
Watch Timer
LCD Controller
SIO
BLD
1/16
IDLE Instruction
CLOCK CIRCUIT
Watch Timer
LCD Controller
Stop
OSCCON.2
System Clock
CPU Clock
7-3