Hitachi SH7751 Hardware Manual page 20

22.6.2 Interrupts from External PCI Devices .................................................................. 921

22.6.3
22.7 Error Detection .................................................................................................................. 922
22.8 PCIC Clock ....................................................................................................................... 922
22.9 Power Management........................................................................................................... 923
22.9.1 Power Management Overview ............................................................................. 923
22.9.2 Stopping the Clock ............................................................................................... 924
22.9.3 Compatibility with Standby and Sleep ................................................................. 927
22.10 Port Functions ................................................................................................................... 927
22.11 Version Management ........................................................................................................ 928
Section 23 Electrical Characteristics
23.1 Absolute Maximum Ratings.............................................................................................. 929
23.2 DC Characteristics............................................................................................................. 930
23.3 AC Characteristics............................................................................................................. 948
23.3.1 Clock and Control Signal Timing ........................................................................ 950
23.3.2 Control Signal Timing.......................................................................................... 961
23.3.3 Bus Timing........................................................................................................... 964
23.3.4 Peripheral Module Signal Timing ..................................................................... 1015
23.3.5 AC Characteristic Test Conditions.................................................................... 1027
23.3.6 Change in Delay Time Based on Load Capacitance ......................................... 1028
Appendix A Address List
Appendix B Package Dimensions
Appendix C Mode Pin Settings
Appendix D Pin Functions
D.1 Pin States ........................................................................................................................ 1044
D.2 Handling of Unused Pins................................................................................................ 1048
Appendix E Synchronous DRAM Address Multiplexing Tables
Appendix F Instruction Prefetching and Its Side Effects
Appendix G Power-On and Power-Off Procedures
Appendix H List of Models
.................................................................................................................... 921
.............................................................................................. 1031
................................................................................... 1041
............................................................................................ 1044
.......................................................................................... 1063
.............................................................................. 929
.............................................................................. 1039
.............................................. 1062
.................... 1050
.................................... 1061
Rev. 3.0, 04/02, page xix of xxxviii