Hitachi SH7751 Hardware Manual page 27

Figure 14.40 Write to Synchronous DRAM (Row Hit) ........................................................ 536
Figure 14.41 Single Address Mode/Burst Mode/External Bus
Block Transfer/Channel 0 On-Demand Data Transfer .................................... 537
Figure 14.42 DDT Mode Setting........................................................................................... 538
Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device
External Bus Data Transfer.............................................................................. 538
Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus
Device Data Transfer ....................................................................................... 539
Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Bus
Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Device
Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer
Request to Channels 1-3 Using Data Bus........................................................ 541
Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus
External Device Data Transfer/ Direct Data Transfer Request to Channel 2
without Using Data Bus ................................................................................... 542
Figure 14.49 Single Address Mode/Burst Mode/External Bus
Transfer/Direct Data Transfer Request to Channel 2....................................... 543
Figure 14.50 Single Address Mode/Burst Mode/External Device
Transfer/Direct Data Transfer Request to Channel 2....................................... 544
Figure 14.51 Single Address Mode/Burst Mode/External Bus
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 . 545
Figure 14.52 Single Address Mode/Burst Mode/External Device
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 . 546
Figure 14.53 Block Diagram of the DMAC.......................................................................... 550
Figure 14.54 DTR Format (Transfer Request Format) (SH7751R) ...................................... 560
Figure 14.55 Single Address Mode/Burst Mode/External Bus
Block Transfer/Channel 0 On-Demand Data Transfer .................................... 565
Figure 14.56 Single Address Mode/Cycle Steal Mode/External Bus
32-Byte Block Transfer/On-Demand Data Transfer on Channel 4.................. 566
Figure 15.1 Block Diagram of SCI ..................................................................................... 571
Figure 15.2 SCK Pin ........................................................................................................... 58 7
Figure 15.3 TxD Pin............................................................................................................ 588
Figure 15.4 RxD Pin............................................................................................................ 588
Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits)...................................................................................... 599
Figure 15.6 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode) ..................................................................................... 601
Figure 15.7 Sample SCI Initialization Flowchart................................................................ 602
Figure 15.8 Sample Serial Transmission Flowchart............................................................ 603
Figure 15.9 Example of Transmit Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)............................................. 605
Rev. 3.0, 04/02, page xxvi of xxxviii

External Device Data Transfer ............................ 539

External Bus Data Transfer ............................ 540

External Device 32-Byte


External

External Device Data

External Bus Data

External Device Data

External Bus Data

External Device 32-Byte

External Device/