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1.6 Configuration of Function Block
1.6.1 Internal block diagram
NMI
INTP0 to INTP6
INTP20 to INTP25
INTP30, INTP31
INTP100, INTP101
INTP110, INTP111
ESO0, ESO1
TO000 to TO005,
TO010 to TO015
TIUD10/TO10,
TCUD10, TCLR10
TIUD11/TO11,
TCUD11, TCLR11
TI2, TCLR2, TO21 to TO24
TI3/TCLR3, TO3
TXD0
RXD0
TXD1
RXD1
ASCK1
TXD2
RXD2
ASCK2
SO0
SI0
SCK0
SO1
SI1
SCK1
CTXD
CRXD
CLK_DBG
SYNC
Note 2
AD0_DBG to AD3_DBG
TRIG_DBG
µ PD703116: 256 KB (mask ROM)
Notes 1.
µ PD70F3116: 256 KB (flash memory)
Incorporated in µ PD70F3116 only.
2.
µ PD703116 is as follows.
TRIG_DBG: IC1, AD0_DBG to AD3_DBG: IC2, SYNC: IC3, CLK_DBG: IC4
µ PD70F3116 only.
3.
µ PD70F3116 only.
4.
In the µ PD703116, the V
CHAPTER 1 INTRODUCTION
ROM
INTC
Note 1
RPU
shifter
TM0: 2 ch
TM1: 2 ch
System
TM2: 2 ch
register
TM3: 1 ch
TM4: 1 ch
RAM
General-
purpose
registers
32bits×32
10 KB
SIO
UART0
BRG0
UART1
BRG1
UART2
BRG2
CSI0
BRG3
Ports
CSI1
FCAN
NBD
Note 3
pin is assigned as the IC5 pin.
PP
User's Manual U14492EJ3V0UD
CPU
BCU
Instruction
PC
queue
32-bit
barrel
Multiplier
32×32
64
ALU
ADC0
ADC1
MEMC
SRAMC
HLDRQ
HLDAK
CS0 to CS7
ROMC
RD
ASTB
UWR
LWR
WAIT
A16 to A23
AD0 to AD15
DMAC
CKSEL
CLKOUT
X1
CG
X2
CV
DD
CV
SS
MODE0 to MODE2
RESET
V
System
DD5
V
SS5
controller
V
DD3
V
SS3
V
PP Note 4
37
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