Programmable Peripheral I/O Registers - NEC V850E/IA1 mPD703116 User Manual

3.4.9

Programmable peripheral I/O registers

In the V850E/IA1, the 16 KB area of x0000H to x3FFFH is provided as a programmable peripheral I/O area. In this
area, the area between x2000H and x2FFFH is used exclusively for the FCAN controller.
The internal bus of the V850E/IA1 becomes active when the on-chip peripheral I/O register area (FFFF000H to
FFFFFFFH) or the programmable peripheral I/O register area (xxxxm000H to xxxxnFFFH) is accessed (m = xx00B, n
= xx11B). However, the on-chip peripheral I/O area is allocated to the last 4 KB of the programmable peripheral I/O
register area. Note that when data is written to this area, the written contents are reflected on the on-chip peripheral
I/O area. Therefore, access to this area is prohibited. To access the on-chip peripheral I/O area, be sure to specify
addresses FFFF000H to FFFFFFFH.
3FFFFFFH
3FFF000H
3FFEFFFH
xxxxNFFFH
xxxxM000H
0000000H
Caution The CAN message buffer register can allocate address xxxx freely as a programmable
peripheral I/O register. But once the address xxxx is set, it cannot be changed.
Remark M = xx00B
N = xx11B
The peripheral area selection control register (BPC) is used for programmable peripheral I/O register area
selection.
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CHAPTER 3 CPU FUNCTION
Figure 3-7. Programmable Peripheral I/O Register (Outline)
On-chip peripheral
I/O register
Programmable
peripheral
I/O register
User's Manual U14492EJ3V0UD
Internal local bus
x3FFFH
On-chip peripheral
I/O area x3000H
x2FFFH
Programmable
x2000H
peripheral
x1FFFH
I/O area
x0000H
Dedicated area for
FCAN controller