Table of Contents
Advertisement
7.3.2 Restore
Recovery from maskable interrupt servicing is carried out by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
(1) Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and
the NP bit of the PSW is 0.
(2) Transfers control to the address of the restored PC and PSW.
Figure 7-5 illustrates the processing of the RETI instruction.
1
Note For the ISPR register, see 7.3.6 In-service priority register (ISPR).
Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during
maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery
by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 0 using
the LDSR instruction immediately before the RETI instruction.
Remark The solid lines show the CPU processing flow.
174
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 7-5. RETI Instruction Processing
RETI instruction
PSW.EP
0
PSW.NP
0
PC
EIPC
PSW
EIPSW
Corresponding
0
Note
bit of ISPR
Restores original processing
User's Manual U14492EJ3V0UD
1
PC
FEPC
PSW
FEPSW
Advertisement
Table of Contents
